IEC 62050-2005 pdf – VHDL Register Transfer Level (RTL) synthesis

IEC 62050-2005 pdf – VHDL Register Transfer Level (RTL) synthesis

IEC 62050-2005 pdf – VHDL Register Transfer Level (RTL) synthesis.
1.3 Terminology The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to). The word should is used to indicate that a certain course of action is preferred but not necessarily required; or that (in the negative form) a cer- tain course of action is deprecated but not prohibited (should equals is recommended that). The word may indicates a course of action permissible within the limits of the standard (may equals is permitted). A synthesis tool is said to accept a VHDL construct if it allows that construct to be legal input; it is said to interpret the construct (or to provide an interpretation of the construct) by producing something that repre- sents the construct. A synthesis tool is not required to provide an interpretation for every construct that it accepts, but only for those for which an interpretation is specified by this standard. The constructs in the standard shall be categorized as follows: Supported: RTL synthesis shall interpret a construct, that is, map the construct to an equivalent hardware representation. Ignored: RTL synthesis shall ignore the construct and produce a warning. Encountering the con- struct shall not cause synthesis to fail, but synthesis results may not match simulation results. The mechanism, if any, by which RTL synthesis notifies (warns) the user of such constructs is not defined by this standard. Ignored constructs may include unsupported constructs. Not Supported: RTL synthesis does not support the construct. RTL synthesis does not expect to encounter the construct, and the failure mode shall be undefined. RTL synthesis may fail upon encountering such a construct. Failure is not mandatory; more specifically, RTL synthesis is allowed to treat such a construct as ignored. NOTE—A synthesis tool may interpret constructs that are identified as not supported in this standard.
2. References This standard shall be used in conjunction with the following publications. When the following standards are superseded by an approved revision, the revision shall apply. IEEE Std 1076.3 TM -1997, IEEE Standard Synthesis Packages (NUMERIC_BIT and NUMERIC_STD). 2, 3 IEEE Std 1164 TM -1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability 3. Definitions and acronyms 3.1 Definitions For the purposes of this standard, the following terms and definitions apply. The Authoritative Dictionary of IEEE Standards Terms, Seventh Edition should be referenced for terms not defined in this clause. Terms used within this standard but not defined in this clause are assumed to be from IEC/IEEE 61691-1-1:2004, IEEE Std 1164-1993, or IEEE Std 1076.3-1997. 5 3.1.1 assignment reference: The occurrence of a literal or expression as the waveform element of a signal assignment statement or as the right-hand side expression of a variable assignment statement. 3.1.2 combinational logic: Logic that settles to a state entirely determined by the current input values and therefore that cannot store information. Any change in the input causes a new state completely defined by the new inputs. 3.1.3 don’t care value: The enumeration literal ‘-’ of the type STD_ULOGIC (or subtype STD_LOGIC).
3.1.9 metalogical value: One of the enumeration literals ‘U’, ‘X’, ‘W’, or ‘-’ of the type STD_ULOGIC (or subtype STD_LOGIC). 3.1.10 pragma: A generic term used to define a construct with no predefined language semantics that influ- ences how a synthesis tool will synthesize VHDL code into an equivalent hardware representation. 3.1.11 sequential logic: Logic that settles to a state not determined solely by current inputs. The current state of such logic can be determined only by knowing the current inputs and some history of past inputs in their sequential order. Sequential logic always stores information from past input and therefore may be used to implement storage elements. 3.1.12 synchronous assignment: An assignment that takes place when a signal or variable value is updated as a direct result of a clock edge expression evaluating as true. 3.1.13 synthesis library: A library of digital design objects such as logic gates, chip pads, memory blocks, or other blocks; instances of these elements are connected together by a synthesis tool to create a synthesized netlist. 3.1.14 synthesis tool: Any system, process, or tool that interprets register transfer level VHDL source code as a description of an electronic circuit and derives a netlist description of that circuit. 3.1.15 synthesis-specific attribute: An attribute recognized by a tool compliant to this standard.

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