BS IEC 62050-2005 pdf – VHDL Register Transfer Level (RTL) synthesis.
1. Overview 1.1 Scope This standard defines a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools. Synthesis tools may be compliant and yet have features beyond those required by this standard. This standard defines how the sem antics of VHDL shall be used, for exam ple, to m odel level-sensitive and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be sup- ported for interoperability. Use of this standard should minim ize the potential for functional sim ulation mismatches between models before they are synthesized and after they are synthesized. 1.2 Compliance to this standard 1.2.1 Model compliance A VHDL m odel shall be defined as being com pliant to this standard if the model a) Uses only constructs described as supported or ignored in this standard b) Adheres to the semantics defined in this standard 1.2.2 Tool compliance A synthesis tool shall be defined as being compliant to this standard if it a) Accepts all models that adhere to the model compliance definition defined in 1.2.1 b) Supports language related pragmas defined by this standard c) Produces a circuit m odel that has the same functionality as the input model based on the verification process as outlined in Clause5.
1.3 Terminology The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to). The word should is used to indicate that a certain course of action is preferred but not necessarily required; or that (in the negative form) a cer- tain course of action is deprecated but not prohibited (should equals is recommended that). The word may indicates a course of action permissible within the lim its of the standard (may equals is permitted). A synthesis tool is said to accept a VHDL construct if it allows that construct to be legal input; it is said to interpret the construct (or to provide an interpretation of the construct) by producing som ething that repre- sents the construct. A synthesis tool is not required to provide an interpretation for every construct that it accepts, but only for those for which an interpretation is specified by this standard. The constructs in the standard shall be categorized as follows: Supported: RTL synthesis shall interpret a construct, that is, map the construct to an equivalent hardware representation. Ignored: RTL synthesis shall ignore the construct and produce a warning. Encountering the con- struct shall not cause synthesis to fail, but synthesis results m ay not match sim ulation results. The m echanism , if any, by which RTL synthesis notifies (warns) the user of such constructs is not defined by this standard. Ignored constructs m ay include unsupported constructs. Not Supported: RTL synthesis does not support the construct. RTL synthesis does not expect to encounter the construct, and the failure mode shall be undefined. RTL synthesis m ay fail upon encountering such a construct. Failure is not mandatory; m ore specifically, RTL synthesis is allowed to treat such a construct as ignored.
2. References This standard shall be used in conjunction with the following publications. W hen the following standards are superseded by an approved revision, the revision shall apply. IEEE Std 1076.3 TM -1997, IEEE Standard Synthesis Packages (NUM ERIC_BIT and NUM ERIC_STD). 2, 3 IEEE Std 1164 TM -1993, IEEE Standard M ultivalue Logic System for VHDL M odel Interoperability 3. Definitions and acronyms 3.1 Definitions For the purposes of this standard, the following term s and definitions apply. The Authoritative Dictionary of IEEE Standards Terms, Seventh Edition should be referenced for term s not defined in this clause. Term s used within this standard but not defined in this clause are assum ed to be from IEC/IEEE 61691-1-1:2004, IEEE Std 1164-1993, or IEEE Std 1076.3-1997. 5 3.1.1 assignment reference: The occurrence of a literal or expression as the waveform element of a signal assignment statement or as the right-hand side expression of a variable assignment statement. 3.1.2 combinational logic: Logic that settles to a state entirely determ ined by the current input values and therefore that cannot store information. Any change in the input causes a new state completely defined by the new inputs. 3.1.3 don’t care value: The enumeration literal ‘-’ of the type STD_ULOGIC (or subtype STD_LOGIC). 3.1.4 edge-sensitive storage element: Any storage elem ent m apped to by a synthesis tool that a) Propagates the value at the data input whenever an appropriate transition in value is detected on a clock control input b) Preserves the last value propagated at all other times, except when any asynchronous control inputs become active (for example, a flip-flop) 3.1.5 high-impedance value: The enumeration literal ‘Z’ of the type STD_ULOGIC (or subtype STD_LOGIC).